System Clock Control Register 0

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	• Overview
	• Oscillation Mode (Power Control Mode)
	• System Clock Control Register 0
	• System Clock Control Register 1
	• Entering Wait Mode
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Power Control

• System Clock Control Register 0

To perform power control, set the System Clock Control Registers 0 and 1, which are assigned in the SFR area. The Protect Register protects these two registers.

1. Selecting the Main Clock Divide Ratio

The Main Clock divide ratio selected after reset is divide-by-8. To change it to another divide ratio, clear the Main Clock (XIN-XOUT) Division Select Bit 0 to 0 in order to enable the Main Clock Division Select Bit 1 in the System Clock Control Register 1.

2. Sub Clock Oscillation

After reset, the Sub Clock is not oscillating. Set the Port XC Select Bit to 1 to let the Sub Clock start oscillating

3. Points to Consider for Reducing the Power Consumption

• Turning Peripheral Functions Off: Before executing the WAIT instruction to enter the Wait Mode, set the WAIT Peripheral Function Clock Stop Bit to 1 in order to turn the unnecessary peripheral functions off.
• Switching the Oscillation Drive Capacity: When clocks are oscillating stably, clear the XIN-XOUT Drive Capacity Select Bit or the XCIN-XCOUT Drive Capacity Select Bit to 0 in order to lower the oscillation drive capacity.

[Main Clock] [Sub Clock] [SFR Area] [XIN-XOUT] [XCIN-XCOUT] [WAIT Instruction] [Wait Mode] [Osc. Drivability Selection] [Protect Register]