4-6-2
#include "prot.h"
#define reserve 0
#pragma section VECT
void (* const vect_table[])(void) = {
reserve, // 0x000 PowerOn reset
reserve, // 0x020 Manual reset
tlbMissR, // 0x040 TLB miss(read)
tlbMissW, // 0x060 TLB miss(write)
firstPageWrite, // 0x080 First Page write
tlbProtectErrorR, // 0x0a0 TLB permition(read)
tlbProtectErrorW, // 0x0c0 TLB permition(write)
addressErrorR, // 0x0e0 Address error(raed)
addressErrorW, // 0x100 Address error(write)
fpuException, // 0x120 FPU exception
tlbDoubleHit, // 0x140 TLB double hits
reserve, // 0x160 TRAPA
illigalInstruction, // 0x180 Illigal instruction
slotIlligal, // 0x1a0 Slot illigal instruction
nmi, // 0x1c0 NMI
userBreak, // 0x1e0 User braek
irl15, // 0x200 IRL15
irl14, // 0x220 IRL14
irl13, // 0x240 IRL13
irl12, // 0x260 IRL12
irl11, // 0x280 IRL11
irl10, // 0x2a0 IRL10
irl9, // 0x2c0 IRL9
irl8, // 0x2e0 IRL8
irl7, // 0x300 IRL7
irl6, // 0x320 IRL6
irl5, // 0x340 IRL5
irl4, // 0x360 IRL4
irl3, // 0x380 IRL3
irl2, // 0x3a0 IRL2
irl1, // 0x3c0 IRL1
@reserve, // 0x3e0 -
tuni0, // 0x400 TUNI0
tuni1, // 0x420 TUNI1
tuni2, // 0x440 TUNI2
ticpi2, // 0x460 TICPI2
ati, // 0x480 RTC
pri, // 0x4a0
cui, // 0x4c0
eri1, // 0x4e0 SCI1
rxi1, // 0x500
txi1, // 0x520
tei1, // 0x540
iti, // 0x560 WDT
rcmi, // 0x580 BSC
rovi, // 0x5a0
reserve, // 0x5c0 -
reserve, // 0x5e0 -
hudi, // 0x600 H-UDI
reserve, // 0x620 -
dei0, // 0x640 DEI0
dei1, // 0x660 DEI1
dei2, // 0x680 DEI2
dei3, // 0x6a0 DEI3
dmae, // 0x6c0 DMAE
reserve, // 0x6e0 -
eri2, // 0x700 SCIF
rxi2, // 0x720
bri2, // 0x740
txi2, // 0x760
reserve, // 0x780 -
reserve, // 0x7a0 -
reserve, // 0x7c0 -
reserve, // 0x7e0 -
fpuDisable, // 0x800 FPU disable
slotFpuDisable, // 0x820 slot FPU disable
reserve, // 0x840 -
trapa0, // 0x860 TRAPA
trapa1,trapa2,trapa3,trapa4,trapa5,trapa6,trapa7,trapa8,trapa9,
trapa10,trapa11,trapa12,trapa13,trapa14,trapa15,trapa16,trapa17,trapa18,trapa19,
trapa20,trapa21,trapa22,trapa23,trapa24,trapa25,trapa26,trapa27,trapa28,trapa29,
trapa30,trapa31,trapa32,trapa33,trapa34,trapa35,trapa36,trapa37,trapa38,trapa39,
trapa40,trapa41,trapa42,trapa43,trapa44,trapa45,trapa46,trapa47,trapa48,trapa49,
trapa50,trapa51,trapa52,trapa53,trapa54,trapa55,trapa56,trapa57,trapa58,trapa59,
trapa60,trapa61,trapa62,trapa63,trapa64,trapa65,trapa66,trapa67,trapa68,trapa69,
trapa70,trapa71,trapa72,trapa13,trapa74,trapa75,trapa76,trapa77,trapa78,trapa79,
trapa80,trapa81,trapa82,trapa83,trapa84,trapa85,trapa86,trapa87,trapa88,trapa89,
trapa90,trapa91,trapa92,trapa93,trapa94,trapa95,trapa96,trapa97,trapa98,trapa99,
trapa100,trapa101,trapa102,trapa103,trapa104,trapa105,trapa106,trapa107,trapa108,trapa109,
trapa110,trapa111,trapa112,trapa113,trapa114,trapa115,trapa116,trapa117,trapa118,trapa119,
trapa120,trapa121,trapa122,trapa123,trapa124,trapa125,trapa126,trapa127,trapa128,trapa129,
trapa130,trapa131,trapa132,trapa133,trapa134,trapa135,trapa136,trapa137,trapa138,trapa139,
trapa140,trapa141,trapa142,trapa143,trapa144,trapa145,trapa146,trapa147,trapa148,trapa149,
trapa150,trapa151,trapa152,trapa153,trapa154,trapa155,trapa156,trapa157,trapa158,trapa159,
trapa160,trapa161,trapa162,trapa163,trapa164,trapa165,trapa166,trapa167,trapa168,trapa169,
trapa170,trapa171,trapa172,trapa173,trapa174,trapa175,trapa176,trapa177,trapa178,trapa179,
trapa180,trapa181,trapa182,trapa183,trapa184,trapa185,trapa186,trapa187,trapa188,trapa189,
trapa190,trapa191,trapa192,trapa193,trapa194,trapa195,trapa196,trapa197,trapa198,trapa199,
trapa200,trapa201,trapa202,trapa203,trapa204,trapa205,trapa206,trapa207,trapa208,trapa209,
trapa210,trapa211,trapa212,trapa213,trapa214,trapa215,trapa216,trapa217,trapa218,trapa219,
trapa220,trapa221,trapa222,trapa223,trapa224,trapa225,trapa226,trapa227,trapa228,trapa229,
trapa230,trapa231,trapa232,trapa233,trapa234,trapa235,trapa236,trapa237,trapa238,trapa239,
trapa240,trapa241,trapa242,trapa243,trapa244,trapa245,trapa246,trapa247,trapa248,trapa249,
trapa250,trapa251,trapa252,trapa253,trapa254,trapa255
} ;
#pragma section
|
4-6-4
#include
#include "iodefine.h"
const unsigned long priority[46][2]={
0,15, //1c0
0,0, //1e0
0,15, //200
0,14, //220
0xffd00010,12, //240
0,12, //260
0,11, //280
0xffd00010,8, //2a0
0,9, //2c0
0,8, //2e0
0xffd00010,4, //300
0,6, //320
0,5, //340
0xffd00010,0, //360
0,3, //380
0,2, //3a0
0,1, //3c0
0,0, //3e0
0xffd00004,12, //400
0xffd00004,8, //420
0xffd00004,4, //440
0xffd00004,4, //460
0xffd00004,0, //480
0xffd00004,0, //4A0
0xffd00004,0, //4C0
0xffd00008,4, //4E0
0xffd00008,4, //500
0xffd00008,4, //520
0xffd00008,4, //540
0xffd00008,12, //560
0xffd00008,8, //580
0xffd00008,8, //5A0
0,0, //5c0
0,0, //5e0
0xffd0000c,0, //600
0xffd0000c,12, //620
0xffd0000c,8, //640
0xffd0000c,8, //660
0xffd0000c,8, //680
0xffd0000c,8, //6a0
0xffd0000c,8, //6c0
0,0, //6e0
0xffd0000c,4, //700
0xffd0000c,4, //720
0xffd0000c,4, //740
0xffd0000c,4, //760
};
#pragma section IRQ
#pragma interrupt(irqHandl)
void irqHandl(void)
{
unsigned int num,mask,irqno;
irqno = EXP.INTEVT >> 5 ;
num = irqno - 0x0e ;
if(INTC.ICR.BIT.IRLM==1){ // interrupt request terminal
mask = *(unsigned short *)(priority[num][0]) ;
mask = mask >> priority[num][1] ;
}
else { //interrupt request revel terminal
switch(num) {
case 0xe:
mask = 15 ;
break ;
default :
if(num < 0x12) //IRL terminal
mask = ((num-2) & 0xf) ^ 0xf ;
else {
mask = *(unsigned short *)(priority[num][0]) ;
mask = mask >> priority[num][1] ;
}
}
}
set_cr((get_cr() & 0xefffff0f)+(mask<<4)) ; // set sr
(vect_table[irqno])() ; // jump interrupt routine
set_cr(get_cr() | 0x10000000) ; // set BL bit
}
#pragma section EXP
#pragma interrupt(expHandl)
void expHandl(void)
{
(vect_table[EXP.EXPEVT>>5])() ; // jump exception routine
}
#pragma section MISS
#pragma interrupt(mmuHandl)
void mmuHandl(void)
{
(vect_table[EXP.EXPEVT>>5])() ; // jump mmu TLB miss routine
}
|
