1-2 Effects of 16-bit instructions

RISC microcomputers are intended to process at higher speeds by simplifying the instruction set. This is based on research that showed that even if complicated instructions are provided, they are seldom used. Complicated operations can be executed by shifting multiple simple instructions, so chip size can be smaller, development costs can be reduced and faster clocks can be used.

In order for a different instruction to be executed in each clock cycle, an instruction per clock cycle must be able to be fetched from memory. For that reason, RISC microcomputers are designed with an instruction length that is less than the internal bus width, to ensure that an instruction is fetched in each clock cycle. Now most 32-bit microcomputers have at least 32-bit internal buses, and most have 32-bit length instructions.

This is how the RISC microcomputer fetches an instruction per clock cycle, then decodes and executes the instruction in the pipeline. The circuits for each stage in the pipeline are separate, so different instructions are in different stagesat the same time.
There are a variety of numbers of stage partitions in different products and the SuperH, excluding the SH-4A, is configured with a 5-stage pipeline, whereas the SH-4A is configured with a 7-stage pipeline.

However, there are two problems with the RISC that uses a 32-bit fixed length instruction set.
One problem is low code density. This is easier to understand if we use operations between registers as an example. When operations are performed between 2 data, most of the bits in the instruction code are unused. In other words, many unused bits are included in the program code, which is a problem. In order to resolve that it is necessary to have a short length instruction set which can be achieve higher code density.

Another problem is that the bus will be a bottleneck. The bus is used to fetch instructions and for data access. In configurations with a single common bus, it can be used for only one of those at a time. If data access is given priority, then the instruction cannot be fetched and it takes 2 clock cycles to fetch the instruction.
To solve both of the problems, the SuperH has adopted 16-bit fixed length instructions. With a 32-bit bus width, 2 instructions can be fetched simultaneously in a single clock cycle , so on a singlescalar SuperH, there is time available in which instructions are not being fetched. Data access can be performed during this time, ensuring single clock cycle execution. Also, a superscalar SuperH can execute 2 commands simultaneously.

In addition, the code density of a 16-bit instruction is higher compared to that of a 32-bit instruction, and is suitable for the on-chip ROM in the single chip computer. It can be seen that the code size is smaller even when compared to other RISC microcomputers.

Also, when microcomputers are sped up, problems can occur during execution of branching. In both RISC and CISC, instructions are read before execution. There is a penalty for the time taken to discard the instruction that was read and fetch instructions from the branch destination.
SuperH solves this problem with delayed branching.
In delayed branching, it branches to the destination after the instruction following the branch instruction has executed. For example, branching which had required 3 clock cycles can be executed in 2 clock cycles in a 5 stage pipeline. The time for branching within instruction execution is said to be reduced by about 30%, so delayed branching has a considerable effect.

The SuperH is a high performance microcomputer even on a smaller chip with 16-bit fixed length instructions giving greater efficiency. However, there are not many general purpose registers that can be specified by instructions. The SuperH can utilize 16 general purpose registers. But that is a fully sufficient number. For example, if we look at an analysis of the number of registers used in motor control programs on a task unit basis, the vast majority use 7 or less. 97% use 16 or less.

The SuperH has an on-chip fixed point multiplication and accumulation unit for DSP function. This unit completes multiplication and accumulation in 2 to 3 clock cycles. Digital filtering, vector operations, discrete cosine transforms and high speed Fourier transforms can be performed faster.
This microcomputer has performance that satisfies a variety of requirements, with 16-bit fixed length instructions and delayed branching for greater speed, and the multiplication and accumulation unit for multimedia.