1. DMAC Overview   The DMAC is a facility that allows data to be transferred at high speed.  It is rarely used alone but is more commonly used in conjunction with an I/O device that requires high-speed data transfer.  Typical applications of the DMAC, for example, might include high-speed data transmission over SCI and high-speed pulse input/output coupled with a timer. The H8/3048 supports a DMAC that allows data to be transferred from memory to memory, from memory to I/O, and from I/O to memory. The DMAC provides up to four channels of data transfer. The DMAC can be started from the CPU, external pins, ITU, and SCI.  Figure 1 is a block diagram of the DMAC.   Figure 1  DMAC block diagram  The DMAC has two modes in which to specify a source and a destination. (1) Short address mode   The DMAC runs as a four-channel (channels 0A/0B/1A/1B) DMAC.  It provides DMA transfer to and from a memory space (including a built-in peripheral) capable of accessing the entire memory space of 16M bytes by 8-bit absolute addressing.   The DMAC can be configured to increment or decrement the memory address on each data transfer request, but the space capable of access by 8-bit absolute addressing can neither be incremented nor decremented.  Normally, a register located in the I/O register is specified.   In short address mode, DMA transfer requests initiated by interrupts originating from the ITU/SCI can be accepted. (2) Full address mode   The DMAC is used as a two-channel (channels 0/1) DMAC.  It allows memory-to-memory data transfer.  It can be configured to increment or decrement the memory address or leave it fixed.  Block transfers can be specified.   Table 1 summarizes the functions of the DMAC.   Table 1  DMAC functions