EDGE RENESAS
 
2006.10/vol.15
BACK NUMBER
Special Feature
Customer Visit
System Solution
Views On
Focus On Packaging
Products Information
Support
Ubiquitous
PDF DOWNLOAD
 
 
SH-Navi2V with Integrated Lane Image-Recognition IP Eases the Way for Road Lane and Other Image-Recognition Applications
The 600MHz single-chip solution is supported by a library of 200 image-recognition routines and a standard platform for CIS applications.
 

Photograph 1: SH-Navi2V(SH7774).

The market for CIS (Car Information System) products is enjoying strong growth with impetus from the increasingly capable car navigation systems consumers are buying for their automobiles. Renesas is the leading global supplier of car navigation SoCs (System on Chip devices). To serve our customers and grow our business, we are releasing the SH-Navi2V SoC, a device that offers more speed and greater functionality, especially image-recognition IP.

 
Building on the success of the SH-Navi1 SoC device
 

Renesas has an overwhelming share of the strongly growing market for car navigation SoCs (System on Chip devices)—60 percent, according to our figures for 2005. This success is due in part to the SH-Navi1 (SH7770) range of SoCs we have been supplying for high-end car navigation systems for some time. Now we aim to bolster that market lead by releasing the SH-Navi2V (SH7774, see Photograph 1). The new single-chip solution uses the SH-4A CPU core that can operate at a maximum of 600MHz. It delivers another big leap in performance: up to 1.5 times the processing capacity of the SH-Navi1 (see Figure 1).

Significantly, the SH-Navi2V is the world's first SoC for car navigation systems to include an integrated image-recognition IP. Beyond that, the sophisticated chip also has a wide range of other peripheral functions, such as a 2D graphics engine and various interfaces, including sound, ATAPI, 10/100Mbps Ethernet, and CAN (see Figure 2).

 

Figure 1: SoC range for CIS applications.

 

Figure 2: Block diagram of SH-Navi2V chip.

 

Processing camera data to produce an output that can be used to increase driver safety

 

The image-recognition IP is a hardware IP module that first performs processing such as edge detection and noise elimination on the image data captured by a camera. Then it applies techniques such as histogram processing on the resulting signal to produce the desired output. The IP was developed in a joint R&D project and is based on the Hitachi Vchip II that was sold as a special-purpose device. This is the first time it has been combined with a CPU in the form of a single-chip SoC. An image-recognition library containing approximately 200 routines is also being released for use with the IP.

Lane recognition and similar vehicle safety applications can be developed using the SH-Navi2V on its own by using the data output from the image-recognition IP in an imaging application. This means that programs that detect aspects of the external environment such as road lanes can be run simultaneously and in real time.

The 2D graphics engine included in the SH-Navi2V chip is packed with functions that are optimized for drawing maps. For example, the thick-line drawing function for drawing roads can draw lines with constant thickness, regardless of their orientation. The graphics engine can also fill connecting sections and process end points. An anti-aliasing function is provided for smoothing the outlines of displayed polygon figures such as parks or schools. A built-in geometry engine helps reduce the load on the CPU by performing calculations such as those required for the coordinates of vertices.

 
Making available a standard platform with CIS peripheral functions
 

The SH-Navi2V SoC includes an internal bus-arbitration circuit to improve the overall performance of the chip. This circuit makes it possible to specify priorities for each internal module that accesses the bus, so that the numerous on-chip functions can access external memory efficiently. Priorities can be set in accordance with the relative importance of different aspects of performance, such as the CPU and graphics. In this way, the user can optimize overall system performance during development based on factors such as configuration and functions.

Renesas offers a Standard Platform to facilitate the design of products that use the SH-Navi2V SoC (see Photograph 2). The platform, which can be used as a test-bed for user systems, includes peripheral functions suitable for CIS applications and allows users to add their own proprietary functions. The test environment uses an E10-USB emulator that connects to the USB port on a host PC. The on-chip debug function of the SH-Navi2V device allows real-time debugging at up to the SoC's 600MHz maximum operating frequency.

For more information, click here.

 

Photograph 2: Standard Platform for the SH-Navi2V.

 
top
Global Site North America Europe Japan Singapore/ASEAN Hong Kong China Taiwan Korea Other Asian
© 2003-2009 Renesas Technology Corp. All rights reserved. Using Our Website | Privacy | Sitemap