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The VPU4 fourth-generation media accelerator IP hardware module can process H.264, MPEG-4, JPEG, and H.263 multimedia data at high speed. It builds on the success of the VPU1, VPU2, and VPU3 now widely used in the popular SH-Mobile processors built into digital cameras, mobile phones and many other type of products. Renesas will incorporate the new IP module into upcoming SH-Mobile series application processors and various image-processing LSI devices.
Flexible processing with high image quality
Prediction techniques are optimized
Fast memory accesses, even to external RAM
Flexible processing with high image quality
The innovative VPU4 (VPU: Video Processing Unit) is a fourth-generation media accelerator IP module. Its key features are flexible media processing, a real-time encoder with high image quality, and low power consumption. The new hardware accelerator supports four data formats: H.264, as well as MPEG-4, JPEG, and H.263. Its design — an evolution of the popular VPU1, VPU2, and VPU3 modules — minimizes the extra chip area needed to process multiple formats by making maximum use of shared circuits, such as those for motion detection and movement compensation.

The VPU4’s H.264 capability is particularly important because that coding format has been chosen for the single-segment broadcasting service expected to be launched next year in Japan. The new service will join the full-scale terrestrial digital broadcasting service now available in the three main Japanese cities.

H.264, also called MPEG-4 AVC (Advanced Video Coding), is an international standard derived from the MPEG-4 standard. It achieves 1.5 to 2 times the compression of MPEG-4, so it can be used to send higher quality video within the same bandwidth. To achieve this performance, though, the H.264 standard imposes more stringent requirements for encoding and decoding. This sophisticated signal processing is best performed by a hardware accelerator. Performing it with software, even on a CPU with strong multimedia performance, would mandate a major increase in clock speed and would be impractical due to power-supply considerations.


VPU Technology Roadmap. The VPU1, VPU2 and VPU3 are incorporated into Renesas SH-Mobile application processors and other chips used in many multimedia systems now in volume production. The new VPU4 expands the capabilities of our product lines, and more VPU IP versions are planned.

Prediction techniques are optimized
The high image quality the VPU4 delivers is an important system design advantage. The new media accelerator optimizes the prediction techniques used in H.264 by using proprietary Renesas algorithms that have been verified through repeated simulations of encoded video. The result is approximately a 1dB improvement in image quality compared to previous VPU versions. Moreover, the VPU4 also supports the VGA encoding image size and a frame rate of 30 frames/sec.

Considerable development effort has been expended to achieve better error processing. Normally, if a bit error occurs during decoding, the image freezes until the next frame signal arrives. The VPU4, however, performs padding when generating the image, ensuring that bit errors don’t interrupt the smoothness of the video replay.

Low power consumption is a particularly important factor for an IP hardware module for chips used in mobile devices. To conserve power, the VPU4 operates at 66MHz and uses techniques such as pipeline processing with clock-control optimization, an approach that lets unused blocks halt their own clock.

Fast memory accesses, even to external RAM
Media accelerator IP modules such as the VPU4 typically require a large working memory. Because Renesas SH-Mobile processors use the SuperHyway high-speed bus, they can achieve fast memory accesses even to external memory. This eliminates the problem of performance loss due to limits on memory access speed. (If external memory is needed, Renesas has a superior solution. We can apply our SIP [Solution Integrated Product] technology to produce a device containing the processor/VPU4 chip and a memory chip. SIPs can provide both high-speed access and space savings.)

Renesas plans to use the VPU4 hardware IP module in image-processing chips and SH-Mobile series application processors. We are also developing a software version that will allow systems equipped with a high-speed microcomputer to perform testing with full software processing. This will eliminate the need to wait until a chip containing the hardware accelerator becomes available.

Whether implemented in hardware or software, our VPU4 IP technology can boost the added value of multimedia systems.


VPU IP modules serve multimedia applications. By adding H.264 baseline encoding/decoding to existing MPEG-4, JPEG, and H.263 support, the VPU4 IP module will enable reception of single-segment terrestrial digital broadcasting, as well as TV telephone functions for mobile phones.

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