System Solution
R & D
Views on
Products Information
International Network
Memory devices with larger capacities and faster speeds are essential for storing audio, video, and other data in digital cameras, mobile phones, notebook PCs and other types of mobile equipment. In December 2003, Hitachi and Renesas announced the AG-AND (Assist Gate-AND) memory cell technology, which was developed to meet this need. The technology uses a 90nm process to achieve the world’s smallest cell size (0.016mm2, equivalent per-bit area) and the world’s fastest write speed for multi-value memory cells (10MB/s). This breakthrough approach will be used in upcoming Renesas 4Gbit flash memory chips.
Kobayashi Takashi
Senior Researcher
ULSI Research Department
Hitachi,Ltd.,Central Research Laboratory
Miniaturization achieved via an Assist Gate structure
Source and drain formed in an "inversion layer"
Miniaturization achieved via an Assist Gate structure
It is now commonplace for flash memory to be used in digital cameras and mobile phones to store still pictures. In the future, it’s anticipated that flash memory applications will extend to include High Vision and other high-resolution video formats, increasing the pressure for greater capacities and faster write speeds. Market demand for flash memory is huge in fields such as digital video cameras, USB storage devices and digital music recorder/players. In commercial video storage equipment, in particular, flash storage capacities are predicted to double in the space of a just a year.

A vital issue for creating higher-capacity flash chips is reducing the size of the device used to store data, in other words the memory cell area. Renesas currently mass produces a 1Gbit AG-AND flash memory, a device based on an AG-AND flash memory cell we jointly developed with Hitachi. It uses our proprietary field-isolation technique, which uses an assist gate (AG) to prevent interference between cells. This approach results in a smaller memory cell area than can be achieved in flash chips that use a trench to separate cells.

When our AG-AND technology is applied to a 1Gbit flash memory manufactured in 130nm technology, the memory cell area is 6F2 , where F is the feature size. Combined with multilevel technology that enables two bits to be stored per cell, the memory cell area is 0.052µm2 (equivalent per bit area), as shown in the photograph on the left in Figure 1, below.

For writing, the AG-AND flash memory uses the hot electron method, which involves injecting the high-energy electrons that are accelerated by the channel electric field to the floating gate (Figure 2). This enables a write time of under 10ms, about an order-of-magnitude faster than the older F-N tunnel method. The assist gate in the AG-AND cell is used to both inject and generate hot electrons with high efficiency. That is, it has two roles: it isolates cells and also improves the efficiency of hot electron injection.


Figure 1: Electron microscope view of AG-AND memory cells. The left side shows the first-generation design (1Gbit, 130nm rule), while the right side shows the second-generation design (4Gbit, 90nm rule).


Figure 2: Writing the cell. Hot-electron injection is used to write the flash cell. In this method, electrons are accelerated by the channel electric field and become high-energy state, "hot", and are injected to the floating gate.

Source and drain formed in an "inversion layer"
The memory cell technology jointly developed by Renesas and Hitachi for the second generation of AG-AND flash memories differs from that used in the first-generation. It employs a technique whereby the assist gate is used to form an inversion layer, then the source and drain of the memory cell transistor are formed on this inversion layer.

The inversion layer is a conductive layer a few nanometers thick that is formed on the surface of the silicon substrate when a voltage is applied to the assist gate. This enables the memory cell area to be reduced to 4F2 from the 6F2 required by the first-generation AG-AND technology. When applied in a 4Gbit memory with a 90nm process, the memory cell size is only 0.016µm2 (equivalent per bit area), the world’s smallest and approximately 30 percent of our first-generation cell. (See photograph on right in Figure 1.)

Again, the write speed is less than 10µs when using a multilevel cell and an assist gate voltage of 7V, and less than 1µs at 8V (Figure 3), according to data from tests using an array test element group (TEG). This indicates that a write speed of 10MB/s will be possible in a 4Gbit memory with a multilevel memory cell.

Takashi Kobayashi, a Senior Researcher at Hitachi’s Central Research Laboratory who was involved in the research, explains the reason for using the inversion layer for the source and drain in the second-generation technology as follows: “The first-generation design used the conventional technique of ion implantation to form a diffusion layer and create the source and drain. However, ion implantation results in significant horizontal spread, and this works against reducing the size of the memory cell as process rule shrink. Our invention is to use the assist gate to form the source and drain. This approach contributes to further miniaturization because the inversion layer only forms on the surface immediately below the assist gate.”

Additional research is ongoing to improve the efficiency of hot electron injection to further boost memory speed.


Figure 3: Memory cell write characteristics for assist gate voltage which form inversion layer.

Global Site North America Europe Japan Singapore/ASEAN Hong Kong China Taiwan Korea Other Asian
© 2010-2012 Renesas Electronics Corporation. All rights reserved. Using Our Website | Privacy | Sitemap