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2004.7/vol.6
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News Releases: From March 25 to June 25, 2004
32-Bit RISC CPU Core Delivers Higher Processing Performance, Better Code Efficiency
Low Power-consumption superSRAM: A Memory Technology Breakthrough
P-channel Power MOSFET’s Low On-resistance Allows Efficient Circuit Designs
PIN Diodes Are Improved Solutions for Transmit/Receive Switching Applications
Scan and Data Drivers Interface to Organic EL Graphic Panels Used in Car Audio Systems
Six-Channel Electronic-Volume-Control ICs Deliver High Audio Quality
Product News: Renesas Takes Part in Joint Development of Cellular RAM Specification
 
SH-2A achieves 360 MIPS at 200MHz, about 3.5 times greater than the SH-2 core, for impressive real-time performance
 
Hitachi and Renesas have jointly developed the SH-2A 32-bit RISC CPU core for real-time control applications in automotive, industrial, and consumer markets. The new core, a development of the popular SH-2 core currently used in many Renesas SuperH-series RISC chips, brings significant improvements in processing performance and program code efficiency. For example, it provides 360MIPS throughput when operating at 200MHz, approximately 3.5 times greater than the SH-2. Processing performance per unit frequency is about 1.4 times better, too, jumping from 1.3MIPS/MHz to 1.8MIPS/MHz. For a specific throughput level, the SH-2A core can operate at a lower clock frequency. This helps reduce power consumption.

A key to these performance improvements is a superscalar architecture that can execute two instructions simultaneously. Also, the core uses separate data and instruction buses that eliminate conflicts between instruction fetch and data access operations, and prevent performance degradations for operations involving repeated memory accesses. The SH-2A’s instruction set is upwardly compatible with that of the SH-2 core, preserving software development investments. It’s more code efficient, too, saving memory space.

Single-chip Renesas microcomputers and SoCs based on the SH-2A CPU core will be announced beginning in the third quarter of 2004. Planned development tools include an optimized C/C++ compiler, as well as SH-2A support for both the compact E10A-USB emulator and the E200F emulator, with built-in profiler function.

For details, please visit our Web site

 
Advanced SRAM design dramatically reduces soft errors, has a small cell size and keeps data retention current low
 

An innovative memory cell design that combines SRAM cell and DRAM capacitor technology reduces the number of soft errors by four orders of magnitude compared with previous Renesas SRAM products. It offers a smaller cell size and lower power consumption, too. The advanced memory cell enables the outstanding performance of our new 16Mbit low-power superSRAM for portable systems and many other applications.

To obtain a high level of resistance to soft errors, at the memory nodes the new cell design uses cylindrical capacitors, like those we have previously used in DRAM cells. A superSRAM built with the cell was the first in the industry to demonstrate no invalid bits due to soft errors in accelerated testing with forced exposure to Alpha rays. The design represents a comprehensive solution to the problem of soft errors associated with miniaturization. Thus, it enables the production of highly reliable, large-capacity SRAMs.

The SRAM cell has two other benefits. It conserves chip area by achieving the industry’s smallest memory cell size for a 0.15?m process SRAM: 0.98?m2. Also, it has a data retention current of less than 1?A, for longer battery life in mobile applications.

Besides using the cell in the 16Mbit superSRAM devices, we will implement it in 32Mbit models planned for introduction later this year.

For details, please visit our Web site

 
The 2.7mΩ(typ.) on-resistance of the HAT1125H is the best available in a SOP-8 package size
 

Renesas has developed a new dual-port static random access memory technology that achieves both the world's smallest cell size per bit (2.04µm2 per bit) and lower power consumption. We will apply this SRAM technology in next-generation microprocessors and SoC (system-on-chip) devices. Trial production in a SRAM built with a 90nm process technology has confirmed the validity of the memory cell design. The test chips also verified a reduction in standby current of approximately 90 percent compared to Renesas' current technology, and a reduction in operating power per unit frequency of about 66 percent.

A new memory cell layout structure was devised to achieve the compact cell size. It uses a shared contact technique whereby a diffusion section and a polycrystalline silicon section for wiring are connected with a single contact. In addition, the structure provides fully shielded bit lines, making it possible to reduce interference noise caused by the fluctuations in electrical signals between adjacent wires.

Standby current is reduced via a "column direction voltage control" method. This design technique decreases not only leakage current but also the cell's operating current.

These results were announced at the 2004 IEEE International Solid-State Circuits Conference in San Francisco.

For details, please visit our Web site

 
HVL147 and HVL147M offer lower pin-to-pin capacitance, on-resistance and second-harmonic distortion
 

Transmit/receive switches in portable devices such as mobile phones and wireless LANs perform better when they are implemented with new Renesas HVL147 and HVL147M PIN diodes. The use of trench construction instead of planar construction, plus optimization of the process and epitaxial layer, produce improvements in all three key diode characteristics: capacitance, on-resistance, and distortion. The pin-to-pin capacitance is only 0.16pF, 15 percent less than the HVL142A, allowing a frequency of 1.8GHz. The on-resistance is decreased by 40 percent to 2.1? at 1mA, and the second-harmonic distortion is improved by 3dB to -45.1dBc at +35dBm.

When these PIN diodes are used as a transmit/receive switch, their lower pin-to-pin capacitance boosts isolation when the switch is off and cuts transfer losses during transmission and reception. It also contributes to lower noise and greater efficiency. Due to their reduced on-resistance, the diodes can be driven with a low bias current, allowing circuit designs that consume less power. The devices’ improved high-order distortion characteristics minimize spurious emissions even at high input levels and also reduce noise.

The leads of the ultra-small and slim package of the HVL147 and HVL147M extend outside the package. This enables solder fillets to be inspected visually after the diodes are mounted on circuit boards, aiding quality control.

For details, please visit our Web site

 
C64665 data driver provides a precision, constant-current output; C64666 scan driver has low on-resistance
 

Two new display drivers are optimized for use with the organic EL graphic panels used in car audio systems and similar applications. The C64665 data driver has 128 push-pull outputs, while the C64666 scan driver has 88. Both support cascade connection in both directions for use with display panels that have higher pixel counts. They are produced with a 0.5µm BiC-DMOS process.

The C64665 uses bipolar elements to construct a high-precision current source. The data driver limits the differences in current between adjacent outputs to less than ±1 percent over a wide range of output currents. This minimizes brightness variation in the graphics panel, allowing a clear display. The output current is set by an external resister and an internal 6-bit D/A converter.

The C64666 scan driver uses DMOS elements. It achieves a low 6.5Ω(typ.) on-resistance in a small, 6.16mm x 2.12mm chip size.

For details, please visit our Web site

 
The M61538FP’s output noise voltage is 0.85mV rms, among the lowest in the industry
 

Three new 6-channel electronic-volume-control ICs provide high audio quality with low noise and low distortion. The multi-channel devices are excellent components for audio equipment designs such as AV amplifiers for home theaters, DVD receivers, and mini-combo systems.

The basic model is the M61538FP, which delivers an output distortion voltage of only 0.85mV rms and a total harmonic distortion of only 0.0012 percent. The M61539FP differs by having a built-in tone control, while the M61540FP provides both a built-in tone control and an input selector.

These volume-control devices output a maximum amplitude of 4.5V rms and can operate from either a single-output or a dual-output (+/-) power supply. They have small packages: The M61538FP is available in a 24-pin SSOP and the M61539FP and M61540FP are available in a 40-pin QFP.

For details, please visit our Web site

 
We will incorporate Cellular RAM technology into MCPs for 2.5G and 3G mobile phones
 

Renesas is collaborating in the joint development of a Cellular RAM standard for pseudo SRAM to be used in 2.5G and 3G mobile phones, along with Cypress Semiconductor Corp., Infineon Technologies AG., and Micron Technology, Inc. The four companies are creating the specification for Cellular RAM products that feature low power consumption, high performance, and low cost. Subsequently, each firm intends to individually develop, manufacture, and market memory devices that conform to the specification and are pin and function compatible.

Cellular RAM is a type of pseudo SRAM that is based on single-transistor DRAM cell technology. The design goal is to achieve a major reduction in chip area compared to standard six-transistor SRAM designs. This will enable the production of chips with greater capacities and lower per-bit prices.

Renesas is the first Asian-based company to be involved in the joint development of the Cellular RAM specification and our participation is expected to boost the adoption of Cellular RAM in Asian markets. When we add Cellular RAM technology to our multi-chip products (MCPs) for mobile phones, an application in which we have extensive experience, we will be able to deliver even better solutions.

Besides working with Cypress, Infineon, and Micron to finalize the Cellular RAM specification, we are developing production devices. We expect to begin shipping samples of 32Mbit and 64Mbit Cellular RAM based products later this year.

For details, please visit our Web site

 
 
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