4-6-2
#include "prot.c"
#define reserve 0
#pragma section VECT
void (* const vect_table[])(void) = {
reserve, // 0x000 reset
reserve, // 0x020 reset
invalidTlbRead, // 0x040 TLB invalid(read)
invalidTlbWrite, // 0x060 TLB invalid(write)
firstPageWrite, // 0x080 First Page write
protectionErrorRead, // 0x0a0 TLB permition(read)
protectionErrorWrite, // 0x0c0 TLB permition(write)
addressErrorRead, // 0x0e0 Address error(raed)
addressErrorWrite, // 0x100 Address error(write)
reserve, // 0x120 -
reserve, // 0x140 -
reserve, // 0x160 TRAPA
illigalInstruction, // 0x180 Illigal instruction
slotIlligalInstruction, // 0x1a0 Slot illigal instruction
nmi, // 0x1c0 NMI
userBreak, // 0x1e0 User braek
irl15, // 0x200 IRL15
irl14, // 0x220 IRL14
irl13, // 0x240 IRL13
irl12, // 0x260 IRL12
irl11, // 0x280 IRL11
irl10, // 0x2a0 IRL10
irl9, // 0x2c0 IRL9
irl8, // 0x2e0 IRL8
irl7, // 0x300 IRL7
irl6, // 0x320 IRL6
irl5, // 0x340 IRL5
irl4, // 0x360 IRL4
irl3, // 0x380 IRL3
irl2, // 0x3a0 IRL2
irl1, // 0x3c0 IRL1
reserve, // 0x3e0 -
tuni0, // 0x400 TUNI0
tuni1, // 0x420 TUNI1
tuni2, // 0x440 TUNI2
ticpi2, // 0x460 TICPI2
ati, // 0x480 RTC ATI
pri, // 0x4a0 PRI
cui, // 0x4c0 CUI
eri, // 0x4e0 SCI ERI
rxi, // 0x500 RXI
txi, // 0x520 TXI
tei, // 0x540 TEI
iti, // 0x560 WDT ITI
rcmi, // 0x580 BSC RCMI
rovi, // 0x5a0 ROVI
dmaAddressError, // 0x5c0 DMA address error
h_udi, // 0x5e0 H-UDI
irq0, // 0x600 IRQ0
irq1, // 0x620 IRQ1
irq2, // 0x640 IRQ2
irq3, // 0x660 IRQ3
irq4, // 0x680 IRQ4
irq5, // 0x6a0 IRQ5
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4-6-3
;Interrupt handler
;VBR + h'600
;
.section INT,code,align=4
mov.l r0,@-sp ;push R0
mov #h'a4,r0 ;set INTEVT2 address
mov.l r1,@-sp ;push R1
shll16 r0
mov.l r2,@-sp ;push R2
shll8 r0
mov.l r3,@-sp ;push R3
mov.l @r0,r0 ;get event code
mov.l r4,@-sp ;push R4
shlr2 r0 ;make jump table offset address
mov.l r5,@-sp ;push R5
shlr r0 ;
mov.l r6,@-sp ;push R6
mov r0,r2 ;copy
mov.l r7,@-sp ;push R7
mov.l #startof CVECT,r1 ;get top address of jump table
sts pr,@-sp ;push PR
add r1,r0 ;
stc spc,@-sp ;push SPC
mov.l @r0,r0 ;get jump address
stc ssr,@-sp ;push SSR
ldc r0,spc ;set jump address
shlr2 r2 ;make priority table address
mova tbl,r0 ;get table top address
add r2,r0 ;top + offset address
mov.b @r0,r0 ;get priority
tst r0,r0 ;test table data,=0 INTEVT,!=0 IPRx
bf sh7708in ;
mov #h'd8,r0 ;set intevt address(H'FFFFFFD8)
mov.l @r0,r0 ;get intevt code
shlr r0 ;change code to interrupt mask data
mov.l #h'f0,r1 ;
extu.b r1,r1 ;
and r1,r0 ;
bra set_sr ;
xor r1,r0 ;
sh7708in:
mov r0,r2 ;copy
shlr r0 ;check bit0
bt/s set_sr ;go to IRL priority
shll r0 ;
shar r2
shar r2
and #2,r0 ;
mov.l #h'fffffee2,r1 ;
add r0,r1 ;
mov.w @r1,r0 ;
shld r2,r0 ;
and #h'f0,r0 ;
set_sr:
mov.l mask,r1 ;get mask data
stc sr,r2
and r2,r1 ;clear interrupt mask bits
or r0,r1 ;set interrupt priority
ldc r1,ssr ;set SSR
mova ret_hnd,r0 ;get return address
lds r0,pr ;set PR
rte ;call
nop ;
;return program
ret_hnd:
mov set_blk,r0 ;get BL bit set data
stc sr,r1 ;
or r1,r0 ;
ldc r0,sr ;exception mask for stack process
ldc @sp+,ssr ;pop
ldc @sp+,spc ;
lds @sp+,pr ;
mov.l @sp+,r7 ;no change RB bit
mov.l @sp+,r6 ;
mov.l @sp+,r5 ;
mov.l @sp+,r4 ;
mov.l @sp+,r3 ;
mov.l @sp+,r2 ;
mov.l @sp+,r1 ;
mov.l @sp+,r0 ;
rte ;return
nop ;
.align 4
mask: .data.l h'efffff0f
set_blk: .data.l h'10000000
;code for priority(interrupt mask)
; bit7 - 4 : shift or priority
; bit3 - 0 : lower address
tbl:
.data.b 0 ;000 Power ON reset
.data.b 0 ;020 Manual reset
.data.b 0,0,0,0,0,0,0,0,0,0,0,0 ;040-1a0
.data.b h'f1 ;1c0 NMI
.data.b 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 ;1e0-3e0
.data.b h'e0 ;400 tuni0
.data.b h'f0 ;420 tuni1
.data.b h'0 ;440 tuni2
.data.b h'0 ;460 ticpi2
.data.b h'10 ;480 ati
.data.b h'10 ;4a0 pri
.data.b h'10 ;4c0 cui
.data.b h'2 ;4e0 eri
.data.b h'2 ;500 rxi
.data.b h'2 ;520 txi
.data.b h'2 ;540 tei
.data.b h'e2 ;560 iti
.data.b h'f2 ;580 rmci
.data.b h'f2 ;5a0 rovi
.data.b 0 ;5c0
.data.b h'f1 ;5e0 H-UDI
.data.b 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 ;600-7e0
.data.b 0,0,0,0,0,0,0,0,0,0,0,0,0 ;800-980
.end
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4-6-4
/*
Interrupt handling program
*/
#include <_h_c_lib.h>
#include "iodefine.h"
#include
void irqHandl(void) ;
void expHandl(void) ;
void mmuHandl(void) ;
extern void (* const vect_table[])(void) ;
const unsigned long priority[14][2]={
0xfffffee2,12, /*400*/
0xfffffee2,8, /*420*/
0xfffffee2,4, /*440*/
0xfffffee2,4, /*460*/
0xfffffee2,0, /*480*/
0xfffffee2,0, /*4A0*/
0xfffffee2,0, /*4C0*/
0xfffffee4,4, /*4E0*/
0xfffffee4,4, /*500*/
0xfffffee4,4, /*520*/
0xfffffee4,4, /*540*/
0xfffffee4,12, /*560*/
0xfffffee4,8, /*580*/
0xfffffee4,8, /*5A0*/
};
#pragma section IRQ
#pragma interrupt(irqHandl)
void irqHandl(void)
{
unsigned int num,mask;
switch(num = INTX.INTEVT2>>5){
case 0xe: // NMI
case 0x2f: // H-UDI
mask = 15 ;
break ;
default:
if((num > 0x2f) | (num < 0x20))
mask = ((INTC.INTEVT>>5) & 0xf)^0xf ;
else {
mask = *(unsigned short *)(priority[(INTC.INTEVT-0x400)>>5][0]) ;
mask = mask >> priority[(INTC.INTEVT-0x400)>>5][1] ;
mask &= 0xf ;
}
}
set_cr((get_cr() & 0xefffff0f)+(mask<<4)) ; // set sr
(vect_table[num])() ; // jump interrupt routine
set_cr(get_cr() | 0x10000000) ; // set BL bit
}
#pragma section EXP
#pragma interrupt(expHandl)
void expHandl(void)
{
(vect_table[INTC.EXPEVT>>5])() ; // jump exception routine
}
#pragma section MISS
#pragma interrupt(mmuHandl)
void mmuHandl(void)
{
(vect_table[INTC.EXPEVT>>5])() ; // jump mmu TLB miss routine
}
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