| 2-7 Characteristics of Instructions |   |
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<Transferring immediate data to registers>
The 8-bit immediate data is contained in instruction code. When transferred to general registers it is sign extended.
16-bit data and 32-bit data are allocated to memory.
This data has the displacement size of 8-bits, so it can be allocated from the current program counter to 256 data area. If it is long word data it can be allocated to the area of up to 1K byte from the program counter. Therefore when a program is large it is divided to secure data fields in between and programs will be connected by unconditional branching instructions. The unconditional branching instructions include return instructions from subroutines.
In the Renesas assembler data of any length can be described as immediate but the assembly results are converted to PC relative.
<Address storage>
It is efficient to use the MOVA instruction to store 32-bit addresses in general registers.
However, only R0 can be specified as the destination for a MOVA instruction.
<Conditional branching instructions>
For conditional branching instructions, when comparing data by specifying conditions using CMP/cond instruction True or False will be displayed as the resulting T bit, then the flow changes using the BT or BF instruction. Data comparison is always done in 32 bits.
8-bit data is sign extended and compared with R0. Immediate data can be compared to R0. Registers other than R0 cannot be used.
16-bit data is extended to 32 bits to be compared.
Signed data is sign extended to 32 bits with the MOV instruction, and can be compared right away.
Unsigned data is compared after signs extended by the MOV instruction are extended to zero.
32-bit data can be compared directly.
MOVA Symbol, R0
Signed 8-bit size displacement can be specified as the branch destination, so BT and BF instructions can branch into up to 128 instructions as shown in the diagram.
<Unconditional branching and subroutine calls>
These instructions branch using PC-relative addressing. Displacement is used for specifying the instructions’ branching destination. Symbols are usually used in programming.
These instructions specify displacement in general registers so branching is possible in any memory space. Therefore it is possible to create position independent programs (object programs that can be allocated to any position in the memory map) in all memory spaces.
These instructions branch at absolute addresses. The instructions are executed after storing the branch destination address as 32 bits in general registers.
These branch instructions are delayed branch instructions.
The instructions allocated to delay slots will definitely be executed with the delayed branch instructions, so instructions should carefully be allocated.
Among conditional branch instructions, BT/S and BF/S are delayed branch instructions.
<Procedure registration>
The stack area is not used to call subroutines. The procedure register stores the return address. Because there is only one procedure register, save the contents of the procedure register to the stack area to nest subroutine calls.
<Multiply instructions and multiply/accumulate instructions>
The multiply instructions and multiply/accumulate instructions store results in the MAC register.
This multiply instruction is a 16-bit x 16-bit = 32-bit operation. There are also double precision multiplication and 32-bit multiplication. The results of any of the operations are stored in the MAC register. The MAC register has a 64-bit structure. This register is a system register and is read using dedicated instructions.
There are word-sized and long word-sized multiply/accumulate instruction operations. MAC instructions multiply between signed integers or between fixed decimal data allocated to memory and add with the MAC register. It is suitable for queue operations or filter operations.
In filter operations the calculation result may overflow and be changed to the wrong symbol due to a calculation precision problem. Therefore the MAC instruction makes it possible to saturate results when overflow or underflow occurs by setting S=1 for the S (Saturation) bit of the Status Register (SR).
<Division instructions>
For division 1-bit division instructions are repeatedly executed. The Div0 instruction prepares for division and the Div1 instruction executes just the number of bits for division.
We’ll show an example of 16-bit division.
Division is performed after upper alignment is done to confirm it is not division by 0.
Functions that are not in the division instruction are performed with other instructions.
The DIV0 instruction initializes M and Q.
The DIV1 instruction outputs the quotient to the T bit.
The DIV1 instruction subtracts the previous T-bit quotient while it takes the R1 dividend from the lower bit. It is easier to understand it as executing subtraction and rotation with the T-bit.
The T bit of the last quotient remains the same so it will be added to the quotient by rotation with the T-bit.
The upper 16 bits is data like a remainder. It can’t be used as it is so it is 0 extended, and treated like the quotient.
Any CPU takes time for division. SuperH executes division by repeating 1-bit division instructions and provides high speed response to interrupt requests.
<Dynamic shift>
There are instructions that allow free changes of shift volumes that use barrel shifters and shift instructions that fix bit numbers. All of the instructions operate within a single clock cycle.
<Privileged instruction>
Instructions that can have a critical effect on the system must be executed in privileged mode. These instructions are called privileged instructions. LDC/STC instructions except for GBR, LDTLB instructions to set MMU, RTE instructions to return from exception handling programs and SLEEP to transfer to low power consumption are privileged instructions.
If they are executed in user mode it will be a violation of privilege and will be transferred to exception handling as a general invalid instruction exception.
<Mode transition>
The CPU has 2 operating modes; privileged and user mode. Change between these 2 modes should be done with care.
Clear the SR.MD bit to change from privileged mode to user mode, and use an exception request to change from user mode to privileged mode.
After reset SH-3 executes programs in privileged mode in P2 area. If you change from privilege mode to user mode with a P2 area address, it will cause an address error. In other words you’ll have to have a U0 area address and then change to user mode. Execute the RTE instruction after setting SPC and SSR to those conditions.
To return to user mode from the called privileged mode, use the RTE instruction. The SR.MD=0 condition that was saved to SSR is restored and it becomes user mode.