9.2 A/D Converter Registers

Table 9.1 shows the A/D converter register configuration.

Table 9.1: A/D Converter Register Configuration

Each register is described below.


(1) A/D control status register (ADCSR)

Figure 9.2 shows the A/D control status register (ADCSR), which selects the channel to be A/D converted, instructs the start of A/D conversion and judges its end.


  *
Figure 9.2: A/D Control Status Register (ADCSR)


Although all 8 bits of this register are capable of reading, indicated by "R" under each bit, certain conditions apply to one of them regarding writing, indicated by "W" in parentheses with "*" attached. The bit marked "W" in parentheses with "*" attached is generally called the "status flag", which requires some precautions. The status flag bit also exists in other internal I/O registers, to which common precautions apply. As for this flag, press the link button shown above ("How to use the status flag") to completely master the use before proceeding.


(2) A/D control register (ADCR)

Figure 9.3 shows the A/D control register (ADCR), which has only one significant bit (bit 7). If this trigger enable bit (TRGE) is not changed from its default value of 0, A/D conversion will not be started even if the trailing edge is input to the ADTRG pin. In this case, conversion can be started by instruction only (setting the ADST of the ADCSR to 1).
If the TRGE is set to 1, on the other hand, A/D conversion can be started by inputting the trailing edge to the ADTRG pin. In this case, however, A/D conversion can also be started by instruction.

Figure 9.3: A/D Control Register (ADCR)

Note: Do not set bit 0 of the ADCR to 1.


(3) A/D data registers A to D (ADDRA to ADDRD)

The 16-bit A/D data registers are designed to store A/D conversion results and located at two consecutive addresses in the memory. Figure 9.4 shows the A/D data register A (ADDRA) as an example. Although the A/D data registers B (ADDRB) to D (ADDRD) have different analog input pins and addresses, the use is completely the same.
Although the ADDRA to ADDRD are 16-bit registers, conversion results are stored in the upper 10 bits. To use only the upper 8 bits of the conversion results, read them in byte-size units. To use all 10 bits of the conversion results, read them in word-size units and handle them by shifting them to the right by 6 bits or by other means.
Figure 9.4: A/D Data Register A (ADDRA)